Timing Model and Specifications
Table 5–32. MAX II Maximum Input Clock Rate for I/O (Part 2 of 2)
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Standard
Unit
3.3-V LVCMOS Without
304
250
220
188
220
188
200
200
150
304
304
250
220
188
220
188
200
200
150
304
304
250
220
188
220
188
200
200
150
304
304
250
220
188
220
188
200
200
150
304
304
250
220
188
220
188
200
200
150
304
MHz
Schmitt Trigger
With Schmitt
Trigger
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5-V LVTTL
Without
Schmitt Trigger
With Schmitt
Trigger
2.5-V LVCMOS Without
Schmitt Trigger
With Schmitt
Trigger
1.8-V LVTTL
Without
Schmitt Trigger
1.8-V LVCMOS Without
Schmitt Trigger
1.5-V LVCMOS Without
Schmitt Trigger
3.3-V PCI
Without
Schmitt Trigger
Table 5–33. MAX II Maximum Output Clock Rate for I/O
–3 Speed
Grade
–4 Speed
Grade
–5 Speed
Grade
–6 Speed
Grade
–7 Speed
Grade
Standard
Unit
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V PCI
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
304
304
220
220
200
200
150
304
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
5–30Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
July 2008
ALTERA [ ALTERA CORPORATION ]
