Timing Model and Specifications
Table 5–26 shows the external I/O timing parameters for EPM2210
devices.
Table 5–26. EPM2210 Global Clock External I/O Timing Parameters
–3 Speed Grade –4 Speed Grade –5 Speed Grade
Symbol
Parameter Condition
Unit
Min
Max
Min
Max
Min
Max
tPD1
Worst case
pin-to-pin
delaythrough
1 look-up
10 pF
10 pF
—
7.0
—
9.1
—
11.2
ns
table (LUT)
tPD2
Best case
pin-to-pin
delaythrough
1 LUT
—
3.7
—
4.8
—
5.9
ns
tSU
tH
Global clock
setup time
—
—
1.2
0.0
2.0
—
—
1.5
0.0
2.0
—
—
1.9
0.0
2.0
—
—
ns
ns
ns
Global clock
hold time
tCO
Global clock
to output
delay
10 pF
4.6
6.0
7.4
tCH
tCL
Global clock
high time
—
—
—
166
166
3.3
—
—
—
216
216
4.0
—
—
—
266
266
5.0
—
—
—
ps
ps
ns
Global clock
low time
tCNT
Minimum
global clock
period for
16-bit
counter
fCNT
Maximum
global clock
frequency for
16-bit
—
—
304.0
(1)
—
247.5
—
201.1
MHz
counter
Note to Table 5–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay
performs faster than this global clock input pin maximum frequency.
5–26Core Version a.b.c variable
MAX II Device Handbook, Volume 1
Altera Corporation
July 2008
ALTERA [ ALTERA CORPORATION ]
