ACEX 1K Programmable Logic Device Family Data Sheet
Table 22. LE Timing Microparameters (Part 2 of 2)
Note (1)
Symbol Parameter
Conditions
tCASC
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
tC
tCO
tCOMB
tSU
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
tH
LE register hold time for data and enable signals after clock
LE register preset delay
tPRE
tCLR
tCH
tCL
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
Table 23. IOE Timing Microparameters
Note (1)
Parameter
13
Symbol
Conditions
tIOD
IOE data delay
IOE register control signal delay
tIOC
tIOCO
tIOCOMB
tIOSU
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
tIOH
IOE register hold time for data and enable signals after clock
IOE register clear time
tIOCLR
tOD1
tOD2
tOD3
tXZ
Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V
Output buffer and pad delay, slow slew rate = off, VCCIO = 2.5 V
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
tZX1
IOE output buffer enable delay, slow slew rate = off, VCCIO = 3.3 V
IOE output buffer enable delay, slow slew rate = off, VCCIO = 2.5 V
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
IOE register feedback delay
C1 = 35 pF (2)
C1 = 35 pF (3)
C1 = 35 pF (4)
tZX2
tZX3
tINREG
tIOFD
tINCOMB
IOE input pad and buffer to FastTrack Interconnect delay
Altera Corporation
55
ALTERA [ ALTERA CORPORATION ]
