ACEX 1K Programmable Logic Device Family Data Sheet
Tables 27 through 29 describe the ACEX 1K external timing parameters
and their symbols.
Table 27. External Reference Timing Parameters
Note (1)
Symbol Parameter
Conditions
Conditions
tDRR
Register-to-register delay via four LEs, three row interconnects, and four local (2)
interconnects
Table 28. External Timing Parameters
Symbol
Parameter
tINSU
Setup time with global clock at IOE register
(3)
(3)
(3)
tINH
Hold time with global clock at IOE register
tOUTCO
tPCISU
tPCIH
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
(3), (4)
(3), (4)
(3), (4)
13
tPCICO
Table 29. External Bidirectional Timing Parameters
Note (3)
Symbol
Parameter
Conditions
tINSUBIDIR
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
tOUTCOBIDIR
tXZBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE register CI = 35 pF
Synchronous IOE output buffer disable delay
CI = 35 pF
CI = 35 pF
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
Notes to tables:
(1) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(2) Contact Altera Applications for test circuit specifications and test conditions.
(3) These timing parameters are sample-tested only.
(4) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.
Altera Corporation
59
ALTERA [ ALTERA CORPORATION ]
