ACEX 1K Programmable Logic Device Family Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
OE Register
PRN
D
Q
Dedicated
Clock
t
t
XZBIDIR
ZXBIDIR
CLRN
t
OUTCOBIDIR
Output Register
PRN
Bidirectional
Pin
D
Q
t
t
INSUBIDIR
CLRN
INHBIDIR
Input Register
PRN
D
Q
CLRN
Tables 29 and 30 show the asynchronous and synchronous timing
waveforms, respectively, for the EAB macroparameters in Table 24.
13
Figure 29. EAB Asynchronous Timing Waveforms
EAB Asynchronous Read
WE
Address
a0
a1
a2
a3
tEABAA
tEABRCCOMB
Data-Out
d0
d1
d2
d3
EAB Asynchronous Write
WE
tEABWP
tEABWDSU
tEABWDH
din0
din1
Data-In
tEABWASU
tEABWAH
tEABWCCOMB
a0
a1
a2
Address
tEABDD
Data-Out
din0
din1
dout2
Altera Corporation
53
ALTERA [ ALTERA CORPORATION ]
