ACEX 1K Programmable Logic Device Family Data Sheet
Figure 30. EAB Synchronous Timing Waveforms
EAB Synchronous Read
WE
Address
CLK
a0
a1
a2
a3
tEABDATASU
tEABDATAH
tEABRCREG
tEABDATACO
Data-Out
d1
d2
EAB Synchronous Write (EAB Output Registers Used)
WE
din1
din2
a2
din3
a3
Data-In
a0
a1
a2
Address
tEABWESU
tEABDATAH
tEABWEH
tEABDATASU
CLK
tEABDATACO
tEABWCREG
dout0
dout1
din1
din2
din3
din2
Data-Out
Tables 22 through 26 describe the ACEX 1K device internal timing
parameters.
Table 22. LE Timing Microparameters (Part 1 of 2)
Note (1)
Symbol Parameter
Conditions
tLUT
LUT delay for data-in
tCLUT
tRLUT
tPACKED
tEN
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
tCICO
Carry-in to carry-out delay
Data-in to carry-out delay
tCGEN
tCGENR
LE register feedback to carry-out delay
54
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
