ACEX 1K Programmable Logic Device Family Data Sheet
Table 26. Interconnect Timing Microparameters
Symbol
Note (1)
Parameter
Conditions
tDIN2IOE
Delay from dedicated input pin to IOE control input
Delay from dedicated input pin to LE or EAB control input
Delay from dedicated input or clock to LE or EAB data
Delay from dedicated clock pin to IOE clock
(7)
(7)
(7)
(7)
(7)
(7)
tDIN2LE
tDIN2DATA
tDCLK2IOE
tDCLK2LE
tSAMELAB
tSAMEROW
Delay from dedicated clock pin to LE or EAB clock
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7)
same row
tSAMECOLUMN Routing delay for an LE driving an IOE in the same column
(7)
tDIFFROW
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7)
row
tTWOROWS
tLEPERIPH
Routing delay for a row IOE or EAB driving an LE or EAB in a different row (7)
Routing delay for an LE driving a control signal of an IOE via the peripheral (7)
control bus
tLABCARRY
tLABCASC
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Notes to tables:
(1) Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
(2) Operating conditions:
(3) Operating conditions:
(4) Operating conditions:
V
V
V
= 3.3 V ± 10% for commercial or industrial and extended use in ACEX 1K devices
= 2.5 V ± 5% for commercial or industrial and extended use in ACEX 1K devices.
= 2.5 V or 3.3 V.
CCIO
CCIO
CCIO
(5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WEsignal is registered.
(6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
(7) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
58
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