ACEX 1K Programmable Logic Device Family Data Sheet
Figure 24 shows the overall timing model, which maps the possible paths
to and from the various elements of the ACEX 1K device.
Figure 24. ACEX 1K Device Timing Model
Dedicated
Clock/Input
Interconnect
I/O Element
Logic
Element
Embedded Array
Block
Figures 25 through 28 show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
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Figure 25. ACEX 1K Device LE Timing Model
Carry-In
Cascade-In
Register
Delays
LUT Delay
tLUT
Data-In
tRLUT
tCLUT
Data-Out
tCO
tCOMB
tSU
tH
Packed Register
Delay
tPRE
tCLR
tPACKED
Register Control
Delay
tC
tEN
Control-In
Carry Chain
Delay
tCGENR
tCGEN
tCICO
tCASC
tLABCARRY
tLABCASC
Carry-Out
Cascade-Out
Altera Corporation
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