ACEX 1K Programmable Logic Device Family Data Sheet
Figure 26. ACEX 1K Device IOE Timing Model
Output Data
Delay
I/O Register
Delays
Output
Delays
tIOD
tIOCO
tIOCOMB
tIOSU
Data-In
tOD1
tOD2
tOD3
tXZ
tIOH
I/O Element
Contol Delay
tIOCLR
tZX1
tZX2
tZX3
Clock Enable
Clear
tIOC
Clock
tINREG
Output Enable
Input Register Delay
I/O Register
Feedback Delay
Data Feedback
into FastTrack
Interconnect
tIOFD
Input Delay
tINCOMB
Figure 27. ACEX 1K Device EAB Timing Model
Input Register
Delays
RAM/ROM
Block Delays
Output Register
Delays
EAB Output
Delay
EAB Data Input
Delays
Data-In
Data-Out
tEABDATA1
tEABDATA2
tEABCO
tEABBYPASS
tEABSU
tEABH
tAA
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABOUT
tDD
Address
tWP
tWDSU
tWDH
tWASU
tWAH
Write Enable
Input Delays
tEABCH
tEABCL
tEABCH
tEABCL
tEABWE1
tEABWE2
WE
tWO
tRP
tRASU
tRAH
EAB Clock
Delay
Input Register
Clock
tEABCLK
Output Register
Clock
Read Enable
Input Delays
tEABRE1
tEABRE2
RE
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Altera Corporation
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