ACEX 1K Programmable Logic Device Family Data Sheet
Table 24. EAB Timing Microparameters
Note (1)
Symbol
Parameter
Conditions
tEABDATA1
tEABDATA2
tEABWE1
tEABWE2
tEABRE1
tEABRE2
tEABCLK
tEABCO
tEABBYPASS
tEABSU
tEABH
Data or address delay to EAB for combinatorial input
Data or address delay to EAB for registered input
Write enable delay to EAB for combinatorial input
Write enable delay to EAB for registered input
Read enable delay to EAB for combinatorial input
Read enable delay to EAB for registered input
EAB register clock delay
EAB register clock-to-output delay
Bypass register delay
EAB register setup time before clock
EAB register hold time after clock
tEABCLR
tAA
EAB register asynchronous clear time to output delay
Address access delay (including the read enable to output delay)
Write pulse width
tWP
tRP
Read pulse width
tWDSU
tWDH
tWASU
tWAH
Data setup time before falling edge of write pulse
Data hold time after falling edge of write pulse
Address setup time before rising edge of write pulse
Address hold time after falling edge of write pulse
Address setup time before rising edge of read pulse
Address hold time after falling edge of read pulse
Write enable to data output valid delay
Data-in to data-out valid delay
(5)
(5)
(5)
(5)
tRASU
tRAH
tWO
tDD
tEABOUT
tEABCH
tEABCL
Data-out delay
Clock high time
Clock low time
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