ACEX 1K Programmable Logic Device Family Data Sheet
Table 25. EAB Timing Macroparameters
Notes (1), (6)
Parameter
Symbol
Conditions
tEABAA
EAB address access delay
tEABRCCOMB
tEABRCREG
tEABWP
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
tEABWCCOMB
tEABWCREG
tEABDD
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
tEABDATACO
tEABDATASU
tEABDATAH
tEABWESU
tEABWEH
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WEsetup time before clock when using input register
EAB WEhold time after clock when using input register
tEABWDSU
EAB data setup time before falling edge of write pulse when not using input
registers
13
tEABWDH
tEABWASU
tEABWAH
tEABWO
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Altera Corporation
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