ACEX 1K Programmable Logic Device Family Data Sheet
Figure 23. Output Drive Characteristics of ACEX 1K Devices
90
90
80
70
IOL
IOL
80
70
60
60
50
40
VCCINT = 2.5 V
VCCIO = 2.5 V
Room Temperature
V
CCINT = 2.5 V
Typical IO
Output
Current (mA)
Typical IO
Output
Current (mA)
VCCIO = 3.3 V
Room Temperature
50
40
30
20
10
30
20
10
IOH
IOH
1
2
3
1
2
3
VO Output Voltage (V)
VO Output Voltage (V)
The continuous, high-performance FastTrack Interconnect routing
resources ensure accurate simulation and timing analysis as well as
predictable performance. This predictable performance contrasts with
that of FPGAs, which use a segmented connection scheme and, therefore,
have an unpredictable performance.
Timing Model
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■
■
■
■
LE register clock-to-output delay (tCO
Interconnect delay (tSAMEROW
LE look-up table delay (tLUT
LE register setup time (tSU
)
)
)
)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the simulator
and Timing Analyzer, or with industry-standard EDA tools. The
Simulator offers both pre-synthesis functional simulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
50
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
