Arria GX Architecture
Table 2–33. EP1AGX60 Device Differential Channels Note (1)
Center Fast PLLs
Corner Fast PLLs
Total
Channels
Package
Transmitter/Receiver
PLL1
PLL2
PLL7
PLL8
Transmitter
29
16
13
17
14
16
13
17
14
21
21
21
21
13
16
14
17
13
16
14
17
21
21
21
21
—
—
—
—
—
—
—
—
21
—
21
—
—
—
—
—
—
—
—
—
21
—
21
—
484-pin FineLine BGA
Receiver
31
29
31
42
42
Transmitter
Receiver
780-pin FineLine BGA
Transmitter
Receiver
1,152-pin FineLine
BGA
Note to Table 2–33:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Table 2–34. EP1AGX90 Device Differential Channels Note (1)
Center Fast PLLs
Corner Fast PLLs
Total
Channels
Package
Transmitter/Receiver
PLL1
PLL2
PLL7
PLL8
Transmitter
45
47
23
22
23
24
22
23
24
23
23
—
23
—
22
—
24
—
1,152-pin FineLine
BGA
Receiver
Note to Table 2–34:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Dedicated Circuitry with DPA Support
Arria GX devices support source-synchronous interfacing with LVDS
signaling at up to 840 Mbps. Arria GX devices can transmit or receive
serial channels along with a low-speed or high-speed clock.
Altera Corporation
May 2008
2–127
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
