High-Speed Differential I/O with DPA Support
Table 2–31. EP1AGX35 Device Differential Channels Note (1)
Center Fast PLLs
Package
Transmitter/Receiver
Total Channels
PLL1
PLL2
Transmitter
29
16
13
17
14
13
16
14
17
780-pin FineLine BGA
Receiver
31
Note to Table 2–31:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Table 2–32. EP1AGX50 Device Differential Channels Note (1)
Center Fast PLLs
Corner Fast PLLs
Total
Channels
Package
Transmitter/Receiver
PLL1
PLL2
PLL7
PLL8
Transmitter
29
31
29
31
42
42
16
13
17
14
16
13
17
14
21
21
21
21
13
16
14
17
13
16
14
17
21
21
21
21
—
—
—
—
—
—
—
—
21
—
21
—
—
—
—
—
—
—
—
—
21
—
21
—
484-pin FineLine BGA
Receiver
Transmitter
Receiver
780-pin FineLine BGA
Transmitter
Receiver
1,152-pin FineLine BGA
Note to Table 2–32:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
2–126
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
