Arria GX Architecture
Figure 2–82. Fast PLL and Channel Layout in the EP1AGX60E and EP1AGX90E Devices Note (1)
Fast
PLL 7
2
4
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
2
2
Fast
PLL 1
Fast
PLL 2
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 8
Note to Figure 2–82:
(1) See Tables 2–30 through 2–34 for the number of channels each device supports.
This chapter references the following documents:
Referenced
Documents
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■
■
■
■
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Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook
Arria GX Transceiver Protocol Support and Additional Features chapter
in volume 2 of the Arria GX Device Handbook
DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook
DSP Blocks in Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook
External Memory Interfaces in Arria GX Devices chapter in volume 2 of
the Arria GX Device Handbook
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook
PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device
Handbook
Altera Corporation
May 2008
2–131
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
