High-Speed Differential I/O with DPA Support
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. The SERDES factor J determines the parallel data width to
deserialize from receivers or to serialize for transmitters. The SERDES
factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL
clock-multiplication W value. A design using the dynamic phase aligner
also supports all of these J factor values. For a J factor of 1, the Arria GX
device bypasses the SERDES block. For a J factor of 2, the Arria GX device
bypasses the SERDES block, and the DDR input and output registers are
used in the IOE. Figure 2–79 shows the block diagram of the Arria GX
transmitter channel.
Figure 2–79. Arria GX Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
+
–
Up to 840 Mbps
10
10
Dedicated
Transmitter
Interface
Local
Interconnect
diffioclk
load_en
refclk
Fast
PLL
Regional or
global clock
Each Arria GX receiver channel features a DPA block for phase detection
and selection, a SERDES, a synchronizer, and a data realigner circuit. You
can bypass the dynamic phase aligner without affecting the basic
source-synchronous operation of the channel. In addition, you can
dynamically switch between using the DPA block or bypassing the block
via a control signal from the logic array.
2–128
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
ALTERA [ ALTERA CORPORATION ]
