Arria GX Architecture
channels that each fast PLL can drive in both I/O banks (I/O Bank 1 and
I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
device, PLL 1 can drive a maximum of 16 transmitter channels in I/O
Bank 2 or a maximum of 29 transmitter channels in I/O Banks 1 and 2.
The Quartus II software can also merge receiver and transmitter PLLs
when a receiver is driving a transmitter. In this case, one fast PLL can
drive both the maximum numbers of receiver and transmitter channels.
1
For more details, refer to the Differential Pin Placement
Guidelines section in the High-Speed Differential I/O Interfaces
with DPA in Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook.
Table 2–30. EP1AGX20 Device Differential Channels Note (1)
Center Fast PLLs
Package
Transmitter/Receiver
Total Channels
PLL1
PLL2
Transmitter
29
16
13
17
14
16
13
17
14
13
16
14
17
13
16
14
17
484-pin FineLine BGA
Receiver
Transmitter
Receiver
31
29
31
780-pin FineLine GBA
Note to Table 2–30:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Table 2–31. EP1AGX35 Device Differential Channels Note (1)
Center Fast PLLs
Package
Transmitter/Receiver
Total Channels
PLL1
PLL2
Transmitter
29
16
13
17
14
13
16
14
17
484-pin FineLine BGA
Receiver
31
Altera Corporation
May 2008
2–125
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
