AV-51002
2017.02.10
1-79
FPP Configuration Timing when DCLK-to-DATA[] >1
FPP Configuration Timing when DCLK-to-DATA[] >1
Table 1-67: FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Arria V Devices
Use these timing parameters when you use the decompression and design security features.
Symbol
Parameter
Minimum
Maximum
600
600
—
1506(98)
1506(99)
—
Unit
ns
ns
µs
µs
µs
µs
µs
ns
s
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
nCONFIGlow to CONF_DONElow
—
—
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
2
nSTATUSlow pulse width
268
—
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time afer rising edge on DCLK
DCLKhigh time
(100)
tCF2CK
1506
2
(100)
tST2CK
tDSU
tDH
—
5.5
—
(101)
N – 1/fDCLK
—
tCH
0.45 × 1/fMAX
—
s
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
fMAX
tR
DCLKperiod
1/fMAX
—
—
s
DCLKfrequency (FPP ×8/ ×16)
Input rise time
125
40
MHz
ns
ns
µs
—
tF
Input fall time
CONF_DONEhigh to user mode(102)
—
40
tCD2UM
175
437
(98)
(99)
is value can be obtained if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
is value can be obtained if you do not delay configuration by externally holding nSTATUSlow.
(100)
(101)
(102)
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATA[]ratio and fDCLK is the DCLKfrequency of the system.
e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V GX, GT, SX, and ST Device Datasheet
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