AV-51002
2017.02.10
1-76
FPGA JTAG Configuration Timing
POR Delay
Minimum
Maximum
Unit
Standard
100
300
ms
Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each configuration scheme.
FPGA JTAG Configuration Timing
Table 1-64: FPGA JTAG Timing Parameters and Values for Arria V Devices
Symbol
Description
Min
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCK clock period
30, 167(92)
TCK clock high time
TCK clock low time
14
14
2
—
—
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
—
3
—
5
—
tJPCO
—
—
—
12(93)
14(93)
14(93)
tJPZX
JTAG port high impedance to valid output
JTAG port valid output to high impedance
tJPXZ
(92)
(93)
e minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if
it equals 1.8 V.
Arria V GX, GT, SX, and ST Device Datasheet
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