AV-51002
2017.02.10
1-78
FPP Configuration Timing when DCLK-to-DATA[] = 1
Symbol
Parameter
Minimum
Maximum
1506(94)
1506(95)
—
Unit
µs
µs
µs
µs
ns
ns
s
tSTATUS
tCF2ST1
nSTATUSlow pulse width
268
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time afer rising edge on DCLK
DCLKhigh time
—
(96)
tCF2CK
1506
(96)
tST2CK
tDSU
2
—
5.5
—
tDH
0
—
tCH
0.45 × 1/fMAX
—
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
DCLKperiod
1/fMAX
—
s
fMAX
tCD2UM
tCD2CU
tCD2UMC
DCLKfrequency (FPP ×8/ ×16)
CONF_DONEhigh to user mode(97)
CONF_DONEhigh to CLKUSRenabled
CONF_DONEhigh to user mode with CLKUSRoption on
—
175
125
437
—
MHz
µs
—
—
4× maximum DCLKperiod
tCD2CU + (Tinit × CLKUSR
—
period)
Tinit
Number of clock cycles required for device initialization
8,576
—
Cycles
Related Information
FPP Configuration Timing
Provides the FPP configuration timing waveforms.
(94)
You can obtain this value if you do not delay configuration by extending the nCONFIGor the nSTATUSlow pulse width.
You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(95)
(96)
(97)
Arria V GX, GT, SX, and ST Device Datasheet
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