AV-51002
2017.02.10
1-77
FPP Configuration Timing
FPP Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[]ratio when you turn on encryption or the compression feature.
Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the DATA[]rate in byte per second (Bps) or word per
second (Wps). For example, in FPP ×16 where the r is 2, the DCLKfrequency must be 2 times the DATA[]rate in Wps.
Table 1-65: DCLK-to-DATA[] Ratio for Arria V Devices
Configuration Scheme
Encryption
Off
Compression
DCLK-to-DATA[] Ratio (r)
Off
Off
On
On
Off
Off
On
On
1
1
2
2
1
2
4
4
On
FPP (8-bit wide)
Off
On
Off
On
FPP (16-bit wide)
Off
On
FPP Configuration Timing when DCLK-to-DATA[] = 1
When you enable decompression or the design security feature, the DCLK-to-DATA[]ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-
to-DATA[]ratio, refer to the DCLK-to-DATA[]Ratio for Arria V Devices table.
Table 1-66: FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Arria V Devices
Symbol
Parameter
nCONFIGlow to CONF_DONElow
Minimum
Maximum
600
Unit
ns
tCF2CD
tCF2ST0
tCFG
—
—
2
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
600
ns
—
µs
Arria V GX, GT, SX, and ST Device Datasheet
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