AV-51002
2017.02.10
1-82
PS Configuration Timing
Symbol
Parameter
Minimum
Maximum
Unit
µs
µs
ns
ns
s
(105)
tCF2CK
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[]setup time before rising edge on DCLK
DATA[]hold time afer rising edge on DCLK
DCLKhigh time
1506
—
—
(105)
tST2CK
tDSU
2
5.5
—
tDH
0
—
tCH
0.45 × 1/fMAX
—
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
DCLKperiod
1/fMAX
—
s
fMAX
tCD2UM
tCD2CU
tCD2UMC
DCLKfrequency
—
175
125
437
—
MHz
µs
—
—
CONF_DONEhigh to user mode(106)
CONF_DONEhigh to CLKUSRenabled
CONF_DONEhigh to user mode with CLKUSRoption on
4 × maximum DCLKperiod
tCD2CU + (Tinit × CLKUSR
—
period)
Tinit
Number of clock cycles required for device initialization
8,576
—
Cycles
Related Information
PS Configuration Timing
Provides the PS configuration timing waveform.
(105)
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
e minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(106)
Arria V GX, GT, SX, and ST Device Datasheet
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