AV-51002
2017.02.10
1-81
DCLK Frequency Specification in the AS Configuration Scheme
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PS Configuration Timing on page 1-81
AS Configuration Timing
Provides the AS configuration timing waveform.
DCLK Frequency Specification in the AS Configuration Scheme
Table 1-69: DCLK Frequency Specification in the AS Configuration Scheme
is table lists the internal clock frequency specification for the AS configuration scheme. e DCLKfrequency specification applies when you use
the internal oscillator as the configuration clock source. e AS multi-device configuration scheme does not support DCLKfrequency of 100 MHz.
Parameter
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
MHz
MHz
MHz
10.6
15.7
31.4
62.9
25.0
DCLKfrequency in AS configuration scheme
21.3
50.0
42.6
100.0
PS Configuration Timing
Table 1-70: PS Timing Parameters for Arria V Devices
Symbol
Parameter
Minimum
Maximum
600
Unit
ns
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
—
—
2
600
ns
—
1506(103)
1506(104)
µs
nSTATUSlow pulse width
268
—
µs
nCONFIGhigh to nSTATUShigh
µs
(103)
(104)
You can obtain this value if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
You can obtain this value if you do not delay configuration by externally holding nSTATUSlow.
Arria V GX, GT, SX, and ST Device Datasheet
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