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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-83  
Initialization  
Initialization  
Table 1-71: Initialization Clock Source Option and the Maximum Frequency for Arria V Devices  
Initialization Clock Source  
Configuration Scheme  
AS, PS, and FPP  
PS and FPP  
Maximum Frequency (MHz)  
Minimum Number of Clock Cycles  
Internal Oscillator  
12.5  
125  
100  
125  
CLKUSR(107)  
Tinit  
AS  
DCLK  
PS and FPP  
Configuration Files  
Table 1-72: Uncompressed .rbf Sizes for Arria V Devices  
Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular  
text file (.ttf) format, have different file sizes.  
For the different types of configuration file and file sizes, refer to the Quartus Prime sofꢂare. However, for a specific version of the Quartus Prime  
sofꢂare, any design targeted for the same device has the same uncompressed configuration file size.  
e IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature.  
(107)  
To enable CLKUSRas the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus Prime  
sofꢂare from the General panel of the Device and Pin Options dialog box.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
 
 
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