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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-80  
AS Configuration Timing  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
tCD2CU  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLKperiod  
tCD2UMC  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (Tinit × CLKUSR  
period)  
Tinit  
Number of clock cycles required for device initialization  
8,576  
Cycles  
Related Information  
FPP Configuration Timing  
Provides the FPP configuration timing waveforms.  
AS Configuration Timing  
Table 1-68: AS Timing Parameters for AS ×1 and ×4 Configurations in Arria V Devices  
e minimum and maximum numbers apply to both the internal oscillator and CLKUSRwhen either one is used as the clock source for device  
configuration.  
e tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS  
Timing Parameters for Arria V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUSlow.  
Symbol  
Parameter  
Minimum  
Maximum  
Unit  
ns  
tCO  
tSU  
DCLKfalling edge to the AS_DATA0/ASDOoutput  
Data setup time before the falling edge on DCLK  
Data hold time afer the falling edge on DCLK  
CONF_DONEhigh to user mode  
2
1.5  
ns  
tDH  
0
175  
ns  
tCD2UM  
tCD2CU  
tCD2UMC  
437  
µs  
CONF_DONEhigh to CLKUSRenabled  
4 × maximum DCLKperiod  
CONF_DONEhigh to user mode with CLKUSRoption on  
tCD2CU + (Tinit × CLKUSR  
period)  
Tinit  
Number of clock cycles required for device initialization  
8,576  
Cycles  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
 
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