AV-51002
2017.02.10
1-74
ARM Trace Timing Characteristics
Figure 1-20: NAND Data Read Timing Diagram
Tcea
NAND_CE
Trr
Trp
Treh
NAND_RE
Trhz
NAND_RB
Trea
NAND_DQ[7:0]
Dout
ARM Trace Timing Characteristics
Table 1-61: ARM Trace Timing Requirements for Arria V Devices
Most debugging tools have a mechanism to adjust the capture point of trace data.
Description
Min
12.5
45
Max
—
55
1
Unit
ns
CLK clock period
CLK maximum duty cycle
CLK to D0 –D7 output data delay
%
–1
ns
UART Interface
e maximum UART baud rate is 6.25 megasymbols per second.
GPIO Interface
e minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. e pulse width is based on a debounce clock frequency of 1 MHz.
Arria V GX, GT, SX, and ST Device Datasheet
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