Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–C7, –I7
–A7
–C8
Unit
Min
80
70
40
20
10
—
Max
200
200
200
200
200
910
Min
80
70
40
20
10
—
Max
200
200
200
200
200
910
Min
80
70
40
20
10
—
Max
200
200
200
200
200
910
×8
×7
×4
×2
×1
—
Mbps
Mbps
Mbps
Mbps
Mbps
ps
SW
Sampling window (high-
speed I/O performance pin)
Sampling window (low-
—
—
1,110
—
1,110
—
1,110
ps
speed I/O performance pin)
(71)
tx Jitter
Input jitter
—
—
—
—
1,000
1
—
—
1,000
1
—
—
1,000
1
ps
tLOCK
Time required for the PLL to
lock, after CONF_DONE
signal goes high, indicating
the completion of device
configuration
ms
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Table 46.
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS receivers are supported at all banks.
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
–A7
–C8
Unit
Min
5
Max
350
360
350
360
Min
5
Max
320
320
320
320
Min
5
Max
320
320
320
320
fHSCLK
Input clock frequency (high-
speed I/O performance pin)
×10
×8
MHz
MHz
MHz
5
5
5
×7
5
5
5
×4
5
5
5
MHz
continued...
(71)
TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
54
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