Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
JTAG Timing Parameters
Table 49.
JTAG Timing Parameters for Intel MAX 10 Devices
The values are based on CL = 10 pF of TDO.
The affected Boundary Scan Test (BST) instructions are SAMPLE/PRELOAD, EXTEST, INTEST, and CHECK_STATUS.
Symbol
Parameter
Non-BST and non-CONFIG_IO Operation
BST and CONFIG_IO Operation
Unit
Minimum
Maximum
Minimum
Maximum
tJCP
40
20
20
2
—
—
—
—
—
—
50
25
25
2
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
TCK clock period
tJCH
TCK clock high time
TCK clock low time
tJCL
tJPSU_TDI
tJPSU_TMS
tJPH
JTAG port setup time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
3
3
10
—
10
—
tJPCO
•
•
15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
•
•
18 (for VCCIO = 3.3, 3.0,
and 2.5 V)
17 (for VCCIO = 1.8 and
1.5 V)
20 (for VCCIO = 1.8 and
1.5 V)
tJPZX
JTAG port high impedance to
valid output
—
—
•
•
15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
—
—
•
•
15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
ns
ns
17 (for VCCIO = 1.8 and
1.5 V)
17 (for VCCIO = 1.8 and
1.5 V)
tJPXZ
JTAG port valid output to high
impedance
•
•
15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
•
•
15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
17 (for VCCIO = 1.8 and
1.5 V)
17 (for VCCIO = 1.8 and
1.5 V)
Intel® MAX® 10 FPGA Device Datasheet
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