Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
–A7
–C8
Unit
Min
5
Max
360
360
700
720
700
720
720
360
150
150
150
150
150
300
300
300
300
300
300
300
510
Min
5
Max
320
320
640
640
640
640
640
320
150
150
150
150
150
300
300
300
300
300
300
300
510
Min
5
Max
320
320
640
640
640
640
640
320
150
150
150
150
150
300
300
300
300
300
300
300
510
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
MHz
MHz
5
5
5
HSIODR
Data rate (high-speed I/O
performance pin)
100
80
70
40
20
10
5
100
80
70
40
20
10
5
100
80
70
40
20
10
5
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
fHSCLK
HSIODR
SW
Input clock frequency (low-
speed I/O performance pin)
5
5
5
MHz
5
5
5
MHz
5
5
5
MHz
5
5
5
MHz
5
5
5
MHz
Data rate (low-speed I/O
performance pin)
100
80
70
40
20
10
—
100
80
70
40
20
10
—
100
80
70
40
20
10
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
Sampling window (high-
speed I/O performance pin)
continued...
Intel® MAX® 10 FPGA Device Datasheet
55
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