Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
–A7
–C8
Unit
Min
Max
Min
Max
Min
Max
Sampling window (low-
—
—
910
—
910
—
910
ps
speed I/O performance pin)
(72)
tx Jitter
Input jitter
—
—
—
—
500
1
—
—
500
1
—
—
500
1
ps
tLOCK
Time required for the PLL to
lock, after CONF_DONE
signal goes high, indicating
the completion of device
configuration
ms
Memory Standards Supported by the Soft Memory Controller
Table 47.
Memory Standards Supported by the Soft Memory Controller for Intel MAX 10 Devices
Contact your local sales representatives for access to the -I6 or -A6 speed grade devices in the Intel Quartus Prime software.
External Memory Interface
Rate Support
Speed Grade
Voltage (V)
Max Frequency (MHz)
Standard
DDR3 SDRAM
DDR3L SDRAM
DDR2 SDRAM
Half
Half
Half
–I6
–I6
1.5
1.35
1.8
303
303
–I6
200
–I7 and –C7
–I6
167
LPDDR2(73)
Half
1.2
200(74)
Related Links
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
(72)
(73)
(74)
TX jitter is the jitter induced from core noise and I/O switching noise.
Intel MAX 10 devices support only single-die LPDDR2.
To achieve the specified performance, constrain the memory device I/O and core power supply variation to within ±3%. By default,
the frequency is 167 MHz.
Intel® MAX® 10 FPGA Device Datasheet
56
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