Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Single Supply Devices LVDS Receiver Timing Specifications
Table 45.
LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices
LVDS receivers are supported at all banks.
Symbol
Parameter
Mode
–C7, –I7
–A7
–C8
Unit
Min
5
Max
145
145
145
145
145
290
290
290
290
290
290
290
100
100
100
100
100
200
200
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
100
100
100
100
100
200
200
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
100
100
100
100
100
200
200
fHSCLK
Input clock frequency (high-
speed I/O performance pin)
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
HSIODR
Data rate (high-speed I/O
performance pin)
100
80
70
40
20
10
5
100
80
70
40
20
10
5
100
80
70
40
20
10
5
fHSCLK
Input clock frequency (low-
speed I/O performance pin)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
HSIODR
Data rate (low-speed I/O
performance pin)
100
100
100
continued...
Intel® MAX® 10 FPGA Device Datasheet
53
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