Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–C7, –I7
–A7
Typ
—
–C8
Typ
—
Unit
Min
80
70
40
20
10
45
Typ
—
Max
200
200
200
200
200
55
Min
80
70
40
20
10
45
Max
200
200
200
200
200
55
Min
80
70
40
20
10
45
Max
200
200
200
200
200
55
×8
×7
×4
×2
×1
—
Mbps
Mbps
Mbps
Mbps
Mbps
%
—
—
—
—
—
—
—
—
—
—
—
—
tDUTY
Duty cycle on
—
—
—
transmitter output
clock
TCCS(67)
Transmitter channel-
to-channel skew
—
—
—
—
300
—
—
300
—
—
300
ps
(68)
tx Jitter
Output jitter
Rise time
—
—
—
1,000
—
—
—
—
1,000
—
—
—
—
1,000
—
ps
ps
tRISE
tFALL
tLOCK
20 – 80%, CLOAD
= 5 pF
500
500
500
Fall time
20 – 80%, CLOAD
= 5 pF
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
Time required for the
PLL to lock, after
—
ms
CONF_DONE signal
goes high, indicating
the completion of
device configuration
(67)
(68)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
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