Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Memory Output Clock Jitter Specifications
Intel MAX 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for Intel MAX 10
devices calibrate automatically.
The memory output clock jitter measurements are for 200 consecutive clock cycles.
The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output
routed on a PHY clock network.
DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.
Table 48.
Memory Output Clock Jitter Specifications for Intel MAX 10 Devices
Parameter
Symbol
–6 Speed Grade
–7 Speed Grade
Unit
Min
Max
127
242
Min
Max
215
360
Clock period jitter
Cycle-to-cycle period jitter
tJIT(per)
tJIT(cc)
–127
—
–215
—
ps
ps
Related Links
Literature: External Memory Interfaces
Provides more information about external memory system performance specifications, board design guidelines, timing
analysis, simulation, and debugging information.
Configuration Specifications
This section provides configuration specifications and timing for Intel MAX 10 devices.
Intel® MAX® 10 FPGA Device Datasheet
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