Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–I6, –A6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Unit
Min
Typ
—
Max
Min
70
40
20
10
45
Max
300
300
300
300
55
Min
70
40
20
10
45
Max
300
300
300
300
55
×7
×4
×2
×1
—
70
40
20
10
45
300
300
300
300
55
Mbps
Mbps
Mbps
Mbps
%
—
—
—
—
—
—
—
—
—
tDUTY
Duty cycle on
—
—
—
transmitter output
clock
TCCS(69)
Transmitter channel-
to-channel skew
—
—
—
—
—
—
300
425
—
—
—
—
300
425
—
—
—
—
300
425
ps
ps
(70)
tx Jitter
Output jitter (high-
speed I/O
performance pin)
Output jitter (low-
speed I/O
—
—
—
470
—
—
470
—
—
470
ps
performance pin)
tRISE
tFALL
tLOCK
Rise time
Fall time
20 – 80%, CLOAD
= 5 pF
—
—
—
500
500
—
—
—
1
—
—
—
500
500
—
—
—
1
—
—
—
500
500
—
—
—
1
ps
ps
20 – 80%, CLOAD
= 5 pF
Time required for the
PLL to lock, after
—
ms
CONF_DONE signal
goes high, indicating
the completion of
device configuration
(69)
(70)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
52
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