Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications
Table 43.
Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
Emulated LVDS_E_3R transmitters are supported at the output pin of all I/O banks.
Symbol
Parameter
Mode
–C7, –I7
–A7
Typ
—
–C8
Typ
—
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
142.5
142.5
142.5
142.5
142.5
285
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
100
100
100
100
100
200
200
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
100
100
100
100
100
200
200
fHSCLK
Input clock frequency
(high-speed I/O
performance pin)
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
×10
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
5
5
—
5
—
5
5
—
5
—
5
5
—
5
—
5
5
—
5
—
5
5
—
5
—
HSIODR
Data rate (high-speed
I/O performance pin)
100
80
70
40
20
10
5
285
100
80
70
40
20
10
5
—
100
80
70
40
20
10
5
—
285
—
—
285
—
—
285
—
—
285
—
—
285
—
—
fHSCLK
Input clock frequency
(low-speed I/O
performance pin)
100
—
—
5
100
5
—
5
—
5
100
5
—
5
—
5
100
5
—
5
—
5
100
5
—
5
—
5
200
5
—
5
—
HSIODR
Data rate (low-speed
I/O performance pin)
100
200
100
—
100
—
continued...
Intel® MAX® 10 FPGA Device Datasheet
49
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