Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–I6
Typ
—
–A6, –C7, –I7
–A7
Typ
—
–C8
Typ
—
Unit
Min
10
Max
360
55
Min
10
Typ
—
Max
Min
10
Max
320
55
Min
10
Max
320
55
×1
—
350
55
Mbps
%
tDUTY
TCCS(65)
tx
Duty cycle on
transmitter output
clock
45
—
45
—
45
—
45
—
Transmitter
channel-to-
channel skew
—
—
—
—
300
—
—
300
—
—
300
—
—
300
ps
Output jitter
Rise time
Fall time
—
—
—
—
—
500
500
—
380
—
—
—
—
—
—
500
500
—
380
—
—
—
—
—
—
500
500
—
380
—
—
—
—
—
—
500
500
—
380
—
ps
ps
(66)
Jitter
tRISE
tFALL
tLOCK
20 – 80%, CLOAD
= 5 pF
20 – 80%, CLOAD
= 5 pF
—
—
—
—
ps
Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
—
1
1
1
1
ms
configuration
(65)
(66)
TCCS specifications apply to I/O banks from the same side only.
TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
48
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