Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
Symbol
Parameter
Mode
–C7, –I7
Typ
–A7
Typ
500
–C8
Typ
500
Unit
Min
Max
Min
Max
Min
Max
tRISE
Rise time
20 – 80%, CLOAD
5 pF
=
=
—
500
—
—
—
—
—
ps
ps
tFALL
Fall time
20 – 80%, CLOAD
5 pF
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
tLOCK
Time required for the
PLL to lock, after
—
ms
CONF_DONE signal
goes high, indicating
the completion of
device configuration
Dual Supply Devices True LVDS Transmitter Timing Specifications
Table 42.
True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
True LVDS transmitter is only supported at the bottom I/O banks.
Symbol
Parameter
Mode
–I6
Typ
—
–A6, –C7, –I7
Max
–A7
Typ
—
–C8
Typ
—
Unit
Min
5
Max
360
360
360
360
360
360
720
720
720
720
720
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
Min
5
Max
Min
5
Max
fHSCLK
Input clock
frequency
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
340
360
340
350
350
350
680
720
680
700
700
310
320
310
320
320
320
620
640
620
640
640
300
320
300
320
320
320
600
640
600
640
640
MHz
MHz
5
—
5
5
—
5
—
5
—
5
5
—
5
—
MHz
5
—
5
5
—
5
—
MHz
5
—
5
5
—
5
—
MHz
5
—
5
5
—
5
—
MHz
HSIODR
Data rate
100
80
70
40
20
—
100
80
70
40
20
100
80
70
40
20
—
100
80
70
40
20
—
Mbps
Mbps
Mbps
Mbps
Mbps
—
—
—
—
—
—
—
—
—
—
—
—
continued...
Intel® MAX® 10 FPGA Device Datasheet
47
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