Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2017.12.15
True LVDS Transmitter Timing
Single Supply Devices True LVDS Transmitter Timing Specifications
Table 41.
True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
True LVDS transmitter is only supported at the bottom I/O banks.
Symbol
Parameter
Mode
–C7, –I7
–A7
Typ
—
–C8
Typ
—
Unit
Min
5
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
145
145
145
145
145
290
290
290
290
290
290
290
55
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
55
Min
5
Max
100
100
100
100
100
200
200
200
200
200
200
200
55
fHSCLK
Input clock frequency
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
—
5
—
5
5
—
5
—
5
5
—
5
—
5
5
—
5
—
5
5
—
5
—
HSIODR
Data rate
100
80
70
40
20
10
45
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
tDUTY
Duty cycle on
transmitter output
clock
—
—
TCCS(63)
Transmitter channel-
to-channel skew
—
—
—
—
—
—
300
—
—
—
—
300
—
—
—
—
300
ps
ps
(64)
tx Jitter
Output jitter
1,000
1,000
1,000
continued...
(63)
TCCS specifications apply to I/O banks from the same side only.
(64)
TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
46
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