[AK4679]
CONTROL SEQUENCE (AUDIO)
■ Clock Set-up
When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied.
1. PLL Master Mode
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Power Supply
PDNA pin
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1)
(1) Power Supply & PDNA and PDNE pins = “L” Æ “H”
(2)
(3)
PMVCM bit
(Addr:00H, D0)
(2)Addr:00H, Data:00H
Addr:03H, Data:F4H
Addr:04H, Data:22H
Addr:05H, Data:02H
PMPLL bit
(Addr:04H, D0)
(4)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:01H
(4)Addr:04H, Data:23H
BICK and LRCK output
(Addr:04H, D1)
10msec(max)
(5)
BICK pin
LRCK pin
Output
Figure 149. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDNA pins = “L” Æ “H”.
“L” time of 1.5μs or more is needed to reset the AK4679.
(2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set.
DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered-up before the other block operates. Power-up time of VCOM is maximum
1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.
(4) PLL lock time is 10ms(max.) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source.
(5) The AK4679 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation
starts.
MS1402-E-06
2013/02
- 205 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
