[AK4679]
Top View
Digital
Ground
Analog
Ground
1k 1k
1k
1k
0.22u
15
0.22u
15
LIN1/IN1+
DMDAT
LIN2/IN2- RIN2/IN2+
LIN3/IN3
RIN3/IN3-
PDNE
HPR
HPL
RIN4
PVDD
CNA
VSS5
CPA
CNB
CPB
RIN1/IN1-/
DMCLK
CSN_SCLE
VSS1
VCOM
AVDD
MPWR1
RCP
VEE
LIN4
VEE
PDNA
SCLA
SYNC1
Line Out
Line In
LOUT/LOP SCLK_CAD0
SDAA
VSS2
ROUT/LON
MPWR2
RCN
SI_CAD1
SO_SDAE
SDOUT2
SDIN4
SYNC2
BCLK1
SDIN1
SDTO
LRCK
TVDDA
BICK
AK4679
JX1_SYNC3
TEST SDOUT3_GP0 SYNCA
SDTOB
SYNCB
BICKB
SDOUT1
SDTI
SVDD
SPN
VSS3
SDIN2
SDOUT4_GP1
TVDDE
SDIN3
SDTIA
DVDD
JX0_BCLK3 STO_RDY
MCKI
VSS3
I2CE
BCLK2
VSS4
BICKA
VDDE
SDTOA
SDTIB
SVDD
SPP
SPFIL
2.2n
Figure 148. Typical Connection Diagram (Analog Input/Output Block)
(In case of Internal Full-differential Mic and External pseudo differential Mic)
Typical signal connections are shown in Figure 38.
MS1402-E-06
2013/02
- 203 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
