[AK4679]
SYSTEM DESIGN
Figure 147 and Figure 148 show the system connection diagram for the AK4679. An evaluation board [AKD4679]
demonstrates the optimum layout, power supply arrangements and measurement results.
Top View
Digital
Ground
Analog
Ground
2.2u
0.1u
2.2u
1.8V
2.2u
LIN2
VSS1
VCOM
AVDD
MPWR1
RCP
RIN2
CSN_SCLE
LOUT
LIN1
RIN1
LIN3
RIN3
HPR
HPL
RIN4
PVDD
CNA
VSS5
CPA
CNB
CPB
VEE
LIN4
VEE
PDNA
SCLA
SYNC1
1u
0.1u
SCLK_CAD0
SI_CAD1
PDNE
SYNC2
SDAA
SDTO
LRCK
SDTOB
SYNCB
BICKB
VSS2
TVDDA
BICK
0.1u
Digital I/O
CODEC
1.6 ∼ 3.6V
Analog
1.7 ∼ 2.0V
ROUT
MPWR2
RCN
BCLK1
SDIN1
10u
AK4679
SO_SDAE JX1_SYNC3
SDOUT2
TEST SDOUT3_GP0 SYNCA
SDTI
SVDD
SPN
VSS3
SDIN4
I2CE
SDIN2
SDOUT4_GP1
TVDDE
SDIN3
SDTIA
DVDD
JX0_BCLK3 STO_RDY
MCKI
SDTOA
SDTIB
VSS3
BCLK2
VSS4
BICKA
VDDE
Analog
3.0 ∼ 5.5V
SVDD
SPP
SPFIL
SDOUT1
10u
0.1u
0.1u
DSP Core
1.1 ∼ 1.3V
0.1u
0.1u
Digital I/O
Digital Core
DSP
1.6 ∼ 3.6V
1.7 ∼ 2.0V
Note:
- VSS1, VSS2, VSS3, VSS4 and VSS5 of the AK4679 should be distributed separately from the ground of
external controllers.
- 0.1μF capacitors at power supply pins should be ceramic capacitors. 2.2μF±50% capacitors between the CPA
to CNA pins, the CPB to CNB pins and the VEE to VSS5 pins should be low ESR ceramic capacitors. These
capacitors must be connected as close as possible to the pins.
Figure 147. Typical Connection Diagram (Power Supply Block)
MS1402-E-06
2013/02
- 202 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
