[AK4679]
7-4. RAM Reading Timing during DSP Reset
Read Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during DSP Reset in the order
of input Command code and Address. PRAM address is fixed to 0h. After writing the Command, the data comes out
from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”) When reading Data
at consecutive address locations, continue to input SCLK as is.
DSPRSTN bit= “0”
CSN
DLRDY bit
SCLK
don’t care
(L/H)
don’t care
(L/H)
Command
Address
SI
Hi-Z or Low
Echo back Output
SO
DATA DATA
DATA
DATA
DATA
Figure 145. RAM Reading at Consecutive Address
7-5. RAM Reading Timing during DSP RUN
Input control register, device identification code, CRC result and error status during both RUN time and DSP Reset
state. These codes are input in the order of Command and Address.
After completing Command code write, the data comes out from the SO pin synchronous with falling edge of
SCLK. (The SI pin input data is “Don’t care”)
DSPRSTN bit=”1”
CSN
DLRDY bit=”0”
SCLK
SI
don’tcare
(L/H)
don’tcare
(L/H)
Command
Address
Hi-Z or Low
SO
Echo Back Output
DATA
Figure 146. RAM Reading during DSP Reset and RUN
MS1402-E-06
2013/02
- 201 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
