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HDMP-1024 参数 Datasheet PDF下载

HDMP-1024图片预览
型号: HDMP-1024
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本的千兆速率发送/接收芯片组与TTL I / O的 [Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os]
分类和应用: 电信集成电路电信电路
文件页数/大小: 40 页 / 316 K
品牌: AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
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Rx Operation Principles  
The HDMP-1024 (Rx) is  
an Input Sampler, a Frame  
loopback (LIN) signal for the  
Input Sampler’s input. If loopback  
enable (LOOPEN) is asserted, the  
LIN input is selected. Also  
included in the Input Selector is  
cable equalization circuitry. When  
coaxial cable is used as the  
transmission media, by setting  
EQEN=1 (enable equalization),  
the equalization circuitry is in the  
DIN signal path and can  
Demultiplexer, a Control Field (C-  
Field) Decoder, and a Data Field  
(D-Field) Decoder. An on-chip  
phase-locked loop (PLL) is used  
to extract timing reference from  
the serial input (DIN or LIN). The  
PLL includes a Phase-Frequency  
Detector, a Loop Filter, and a  
variable-frequency oscillator  
(VCO). All the RX internal clock  
signals are generated from a  
Clock Generator. The Clock  
Generator can be driven either by  
internal VCO or external signal,  
TCLK, depending on the Clock  
Select configuration.  
monolithically implemented in a  
high performance 25 GHz ft  
bipolar process. When properly  
configured, the Rx can accept  
20B/24B CIMT line code frames,  
and then output parallel 16B/17B/  
20B/21B Data Word or 14B/18B  
Control Word. The Rx provides  
the following functions for link  
operation:  
compensate for high-frequency  
cable loss.  
• Clock recovery  
• Frame synchronization  
• Data recovery  
Because the Data Field of the  
CIMT line code can be either  
16-bit or 20-bit wide, the width  
selection for Rx is made by  
setting the input pin M20SEL  
(Figure 5). If M20SEL=1, then  
the Rx is configured to accept  
serial input with 20-bit data field,  
i.e., 24 bits per frame. If  
• Demultiplexing  
• Frame decoding  
• Frame error detection  
• Link state control  
Integrated on the chip is a Link-  
Control State Machine for link  
status monitoring and link  
startup. Figure 13 shows the  
details of the Input Select. The  
Input Select chooses either  
nominal serial data (DIN) or  
Rx Encoding  
Figure 5 shows a simplified block  
diagram of the receiver. The data  
path consists of an Input Select,  
M20SEL = 0, 16-bit data field is  
selected.  
LOOPEN  
EQEN  
0
DIN  
0
1
CABLE EQ  
SIN  
1
LIN  
Figure 13. HDMP-1024 (Rx) Input Selector.  
643  
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