Data Sheet
AD5940
Sequence 3 Information Register—SEQ3INFO
Address 0x000021E4, Reset: 0x00000000, Name: SEQ3INFO
Table 108. Bit Descriptions for SEQ3INFO Register
Bits
Bit Name
Reserved
INSTNUM
Reserved
STARTADDR
Settings
Description
Reserved.
SEQ3 instruction number.
Reserved.
SEQ3 start address.
Reset
0x0
0x0
0x0
0x0
Access
R
R/W
R
[31:27]
[26:16]
[15:11]
[10:0]
R/W
Sequence 1 Information Register—SEQ1INFO
Address 0x000021E8, Reset: 0x00000000, Name: SEQ1INFO
Table 109. Bit Descriptions for SEQ1INFO Register
Bits
Bit Name
Reserved
SEQ1INSTNUM
Reserved
SEQ1STARTADDR
Settings
Description
Reserved.
SEQ1 instruction number.
Reserved.
SEQ1 start address.
Reset
Access
R
R/W
R
[31:27]
[26:16]
[15:11]
[10:0]
0x0
0x0
0x0
0x0
R/W
Command and Data FIFO Internal Data Count Register—FIFOCNTSTA
Address 0x00002200, Reset: 0x00000000, Name: FIFOCNTSTA
Table 110. Bit Descriptions for FIFOCNTSTA Register
Bits
Bit Name
Reserved
DATAFIFOCNTSTA[10:0]
Reserved
Settings
Description
Reserved.
Current number of words in the data FIFO
Reserved
Reset
0x0
0x0
Access
[31:27]
[26:16]
[15:0]
R
R
R
0x0
Sync External Devices Register—SYNCEXTDEVICE
Address 0x00002054, Reset: 0x00000000, Name: SYNCEXTDEVICE
Table 111. Bit Descriptions for SYNCEXTDEVICE Register
Bits
[31:8] Reserved
[7:0] Sync
Bit Name Settings Description
Reset Access
Reserved.
0x0
0x0
R
R/W
Output data of the GPIOx. Refer to the GP0CON register for information on how the
GPIOx is controlled. Writing 1 to the corresponding bit sets the corresponding GPIOx
high. Writing 0 sets the corresponding GPIOx to 0.
Trigger Sequence Register—TRIGSEQ
Address 0x00000430, Reset: 0x0000, Name: TRIGSEQ
Table 112. Bit Descriptions for TRIGSEQ Register
Bits
[15:4]
3
2
1
0
Bit Name
Reserved
TRIG3
TRIG2
TRIG1
Settings
Description
Reserved.
Trigger Sequence 3.
Trigger Sequence 2.
Trigger Sequence 1.
Trigger Sequence 0.
Reset
Access
R
R/W
R/W
R/W
R/WS
0x0
0x0
0x0
0x0
0x0
TRIG0
Rev. 0 | Page 91 of 130
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