AD5940
Data Sheet
Sequence 2 Information Register—SEQ2INFO
Address 0x000021D0, Reset: 0x00000000, Name: SEQ2INFO
Table 104. Bit Descriptions for SEQ2INFO Register
Bits
Bit Name
Reserved
SEQ2INSTNUM
Reserved
SEQ2STARTADDR
Settings
Description
Reserved.
SEQ2 instruction number.
Reserved.
SEQ2 start address.
Reset
0x0
0x0
0x0
0x0
Access
R
R/W
R
[31:27]
[26:16]
[15:11]
[10:0]
R/W
Command FIFO Write Address Register—CMDFIFOWADDR
Address 0x000021D4, Reset: 0x00000000, Name: CMDFIFOWADDR
Table 105. Bit Descriptions for CMDFIFOWADDR Register
Bits
[31:11]
[10:0]
Bit Name
Reserved
WADDR
Settings
Description
Reserved.
Reset
0x0
0x0
Access
R
R/W
Write address. These bits are the address in SRAM in which to store the command.
Command Data Control Register—CMDDATACON
Address 0x000021D8, Reset: 0x00000410, Name: CMDDATACON
Table 106. Bit Descriptions for CMDDATACON Register
Bits
[31:12]
[11:9]
Bit Name
Reserved
Settings
Description
Reserved.
Reset
0x0
Access
R
DATAMEMMDE
Data FIFO mode select.
0x2
R/W
10 FIFO mode.
11 Stream mode.
Data FIFO size select.
[8:6]
DATA_MEM_SEL
0x0
R/W
000 Reserved.
001 2 kB SRAM.
010 4 kB SRAM.
011 6 kB SRAM.
[5:3]
[2:0]
CMDMEMMDE
CMD_MEM_SEL
Command FIFO mode.
01 Memory mode.
10 Reserved.
0x2
0x0
R/W
R/W
11 Reserved.
Command memory select.
0x0 Reserved.
0x1 2 kB SRAM.
0x2 4 kB SRAM.
0x3 6 kB SRAM.
Data FIFO Threshold Register—DATAFIFOTHRES
Address 0x000021E0, Reset: 0x00000000, Name: DATAFIFOTHRES
Table 107. Bit Descriptions for DATAFIFOTHRES Register
Bits
Bit Name
Reserved
HIGHTHRES
Reserved
Settings
Description
Reserved.
High threshold.
Reserved.
Reset
0x0
0x0
Access
R
R/W
R
[31:27]
[26:16]
[15:0]
0x0
Rev. 0 | Page 90 of 130
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