Data Sheet
AD5940
Data FIFO Read Register—DATAFIFORD
Address: 0x0000206C, Reset: 0x00000000, Name: DATAFIFORD
Table 99. Bit Descriptions for DATAFIFORD Register
Bits
[31:16] Reserved
[15:0] DATAFIFOOUT
Bit Name
Settings Description
Reset
0x0
Access
R
R
Reserved.
Data FIFO read. If the data FIFO is empty, a read of this register returns 0x00000000. 0x0
Command FIFO Write Register—CMDFIFOWRITE
Address 0x00002070, Reset: 0x00000000, Name: CMDFIFOWRITE
Table 100. Bit Descriptions for CMDFIFOWRITE Register
Bits
Bit Name
Settings Description
Command FIFO write. If the command FIFO is written when full, the write is ignored
and all current commands are not affected.
Reset Access
0x0
[31:0] CMDFIFOIN
W
Sequencer Sleep Control Lock Register—SEQSLPLOCK
Address 0x00002118, Reset: 0x00000000, Name: SEQSLPLOCK
The SEQSLPLOCK register protects the SEQTRGSLP register.
Table 101. Bit Descriptions for SEQSLPLOCK Register
Bits
[31:20] Reserved
[19:0] SEQ_SLP_PW
Bit Name
Settings Description
Reset Access
Reserved.
0x0
0x0
R
Password for the SEQTRGSLP register. These bits prevent the sequencer from
R/W
accidentally triggering a sleep state.
0x0000 Write any value other than 0xA47E5 to lock the SEQTRGSLP register.
0xA47E5 Write this value to this register to unlock the SEQTRGSLP register.
Sequencer Trigger Sleep Register—SEQTRGSLP
Address 0x0000211C, Reset: 0x00000000, Name: SEQTRGSLP
The SEQTRGSLP register is protected by the SEQSLPLOCK register.
Table 102. Bit Descriptions for SEQTRGSLP Register
Bits
[31:1] Reserved
TRGSLP
Bit Name
Settings Description
Reset Access
Reserved.
0x0
R
0
Trigger sleep by sequencer. Write to the SEQSLPLOCK register first. Put this command 0x0
at the end of a sequence. Set this command to 1 if entering sleep at the end of a
sequence.
R/W
Sequence 0 Information Register—SEQ0INFO
Address 0x000021CC, Reset: 0x00000000, Name: SEQ0INFO
Table 103. Bit Descriptions for SEQ0INFO Register
Bits
Bit Name
Reserved
SEQ0INSTNUM
Reserved
SEQ0STARTADDR
Settings
Description
Reserved.
SEQ0 instruction number.
Reserved.
SEQ0 start address.
Reset
0x0
0x0
0x0
0x0
Access
R
R/W
R
[31:27]
[26:16]
[15:11]
[10:0]
R/W
Rev. 0 | Page 89 of 130
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