AD5940
Data Sheet
development kit. The sequencer can also access the GPIO when
running. This access synchronizes external devices, such as the
ADXL362 or the AD8233. To perform this synchronization, the
corresponding GPIOx functionality must be set to synchronize
in the GP0CON register and the direction of data must be set to
output in the GP0OEN register. The sequencer can then write
to the SYNCEXTDEVICE register to toggle the corresponding
GPIOx pin, which is a useful debugging feature when
programming the sequencer.
Data FIFO Word Format
The format of data FIFO words is shown in Figure 39. Each
word in the data FIFO is 32 bits. The seven MSBs are the error
correction code (ECC) required for functional safety applications.
Bits[24:23] of the data FIFO word form the sequence ID and
indicate which sequence, from SEQ0 to SEQ3, the result came
from.
Bits[22:16] of the data FIFO word contain the channel ID and
indicate the source for the data (see Table 92).
Sequencer Conflicts
The 16 LSBs of the data FIFO word are the actual data (see
Figure 39).
If a conflict between sequences arises, for example, when SEQ0
is running and the SEQ1 request arrives, SEQ1 is ignored and
SEQ0 completes. An interrupt is generated to indicate that the
SEQ1 sequence is ignored.
When the data source is the DFT result, the data is 18 bits wide and
is in twos complement format. The format is shown in Figure 40.
The channel ID is five bits wide, with 5’b11111 indicating the
DFT results.
Reading back registers does not cause resource conflicts. Writes
to the MMRs by the host controller are allowed when the
sequencer is enabled. There can be some conflicts. If conflicts
arise, the sequencer has the priority. If the sequencer and the
host controller write at the same time, the host controller is
ignored. There is no error report for this conflict. The user must
not write to a register when the sequencer is running. However,
there are exceptions, which can be written to freely without any
conflict. The SEQCON register allows ending sequence
Sequencer and the Sleep and Wake-Up Timer
See the Sleep and Wake-Up Timer section for more information.
Configuring the GPIOx Pin Mux
Each of the eight GPIOx pins can be configured to trigger a
sequence. The GPIOx pin must first be configured as an input
in the GP0OEN register. Then, the pin must be configured to
the PINxCFG bits in the GP0CON register. Register EI0CON
and EI1CON configure how to detect a GPIO event, either level
triggered or edge triggered. After a GPIO event is detected, the
corresponding sequence runs. Refer to the
execution (SEQEN bit) and halting a sequence (SEQHALT bit).
AD5940_SEQGpioTrigCfg function in the AD5940 software
Table 92. Channel ID Description
Bits[22:16] of the Data FIFO Word
Description
11111 xx
11110xx
11101xx
1xxxxxx
0xxxxxx
DFT result
Mean from statistics block
Variance from statistics block
Sinc2 filter result, xxxxxx is the ADC multiplexer positive setting (ADCCON [5:0])
Sinc3 filter result, xxxxxx is the ADC multiplexer positive setting (ADCCON [5:0])
[31:25]
[24:23]
[22:16]
CH_ID
[15:0]
2-BIT
SEQ
ID
7-BIT
ECC
16-BIT
DATA
Figure 39. Data FIFO Word Format
[31:25]
[24:23]
[22:18]
[17:0]
2-BIT
SEQ
ID
7-BIT
ECC
CH_ID
5'b11111
18-BIT
DATA
Figure 40. Data FIFO DFT Word Format
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