Data Sheet
AD5940
There are a number of interrupt sources associated with the
sequencer, including the following:
SEQUENCER OPERATION
Figure 38 shows the typical steps required to set up the sequencer
to take measurements. After the device is booted, the sequencer,
command memory, and data FIFO must be configured. The
following steps are required for this configuration:
•
•
•
Sequence timeout error.
Sequencer timeout command finished.
End of sequence interrupt. For this interrupt to be asserted,
SEQCON, Bit 0, must be cleared at the end of the sequencer
command.
1. Configure the command memory.
2. Load the sequences into SRAM.
3. Set the Sequence 0 (SEQ0) to Sequence 3 (SEQ3)
information sequences.
Refer to the Interrupts section for more information.
Data FIFO
4. Configure the data FIFO.
The data FIFO provides a buffer for the output of the analog
and DSP blocks before it is read by the external controller.
5. Configure the sleep wake-up timer.
6. Configure the GPIO pin mux.
7. Configure the interrupts.
The memory available for the data FIFO can be selected in the
DATA_MEM_SEL bits in the CMDDATACON register. The
available options are 2 kB, 4 kB, and 6 kB. The data FIFO and
command memory share the same block of 6 kB SRAM. Therefore,
ensure there is no overlap between the command memory and
data FIFO.
8. Configure the sleep and wake-up method.
Command Memory
The command memory stores the sequence commands and
provides a link between the external microcontroller and the
sequencer. The command memory can be configured to use the
2 kB, 4, kB, and 6 kB SRAM memory sizes, which are selected using
the CMDDATACON, Bits[2:0].
The data FIFO can be configured in FIFO mode or stream mode
via CMDDATACON, Bits[11:9]. In stream mode, when the FIFO
is full, old data is discarded to make room for new data. In FIFO
mode, when the FIFO is full, new data is discarded. Never let
the FIFO overflow when in FIFO mode. All new data are then lost.
The large amount of memory available for the command memory
facilitates the creation of larger, more complex sequences.
Determine the number of commands in a sequence by reading
SEQxINFO, Bits[26:16].
The data FIFO is always unidirectional. A selectable source in
the AFE block writes data and the external microcontroller
reads data from DATAFIFORD.
The command memory is unidirectional. The host microcontroller
specifies the destination address of the command by writing to
the CMDFIFOWADDR register and writes the command contents
to the CMDFIFOWRITE register. The sequencer reads the
commands from memory for execution.
Select the data source for the data FIFO in DATAFIFOSRCSEL
(FIFOCON, Bits[15:13]). The available options are as follows:
ADC data, DFT result, sinc2 filter result, statistic block mean
result, and statistic block variance result.
There are a number of interrupts associated with the command
FIFO, including the FIFO threshold interrupt, the FIFO empty
interrupt, and the FIFO full interrupt. Refer to the Interrupts
section for more information.
There a number of interrupt flags associated with the data
FIFO, including the following: empty, full, overflow, underflow,
and threshold.
These interrupts are user readable using the INTCFLAGx
registers (see the Interrupts section for more details). Each flag
has an associated maskable interrupt.
Loading Sequences
The sequence commands are written to SRAM by writing to
two registers. The address in SRAM for the command is written
to the CMDFIFOWADDR register. The command content is
written to the CMDFIFOWRITE register. After all the
commands are written to SRAM, set the SEQ0 to SEQ3
information sequences by writing to the SEQxINFO registers.
The overflow and underflow flags only activate for one clock
period.
The data FIFO is enabled by writing a 1 to FIFOCON, Bit 11.
The data FIFO threshold value is set by writing to the
DATAFIFOTHRES register. At any time, the host
microcontroller can read the number of words in the data FIFO
by reading FIFOCNTSTA, Bits[26:16].
Each information sequence from SEQ0 to SEQ3 requires a start
address in SRAM and a total number or commands for that
sequence. The number of commands is written to SEQxINFO,
Bits[26:16]. The start address is written to SEQxINFO,
Bits[10:0]. Ensure there is no overlap between the four
sequences. There is no hardware mechanism in place to warn
the user of overlapping sequences.
Reading data from the data FIFO when empty returns
0x00000000. In addition, the underflow flag, FLAG27, in the
INTCFLAGx register is asserted.
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