Data Sheet
AD5940
SEQUENCER
The number of commands executed by the sequencer can be
SEQUENCER FEATURES
read from the SEQCNT register. Each time a command is read
from command memory and executed, the counter is increments
by 1. Performing a write to the SEQCNT register resets the counter.
The features of the AD5940 sequencer are as follows:
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Programmable for cycle accurate applications.
Four separate command sequences.
Large 6 kB SRAM to store sequences.
FIFO for storing measurement results.
Control via the wake-up timer, SPI command, or GPIO
toggle.
The sequencer calculates the cyclic redundancy check (CRC) of
all commands it executes. The algorithm used is the CRC-8, using
the x8 + x2 + x + 1 polynomial. The CRC-8 algorithm performs
on 32-bit input data (sequencer instructions). Each 32-bit input
is processed in one clock cycle and the result is available
immediately for reading by the host controller. The CRC value
can be read from the SEQCRC register. This register is reset by
the same mechanism as the command count, by writing to the
SEQCNT register. The SEQCRC resets to a seed value of 0x01.
SEQCRC is a read only register.
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Various interrupts from user maskable sources.
SEQUENCER OVERVIEW
The role of the sequencer is to allow offloading of the low level
AFE operations from the external microcontroller and to
provide cyclic accurate control over the analog DSP blocks. The
sequencer handles timing critical operations without being
subject to system load.
SEQUENCER COMMANDS
There are two types of commands that can be executed by the
sequencer: write commands and timer commands, which
includes wait commands and timeout commands.
In the AD5940, four sequences are supported by hardware.
These sequences can be stored in SRAM to easily switch between
different measurement procedures. Only one sequence can be
executed by the sequencer at a time. However, the user can
configure which sequences the sequencer executes and the
order in which they are executed.
Write Command
Use a write instruction to write data into a register. The register
address must lie between 0x00000000 and 0x000021FC.
Figure 35 shows the format of the instruction. The MSB is equal
to 1, which indicates a write command.
The sequencer reads commands from the sequence that is
stored in the command memory and, depending on the
command, either waits a certain amount of time or writes a
value to a memory map register (MMR). The execution is
sequential, with no branching. The sequencer cannot read
MMR values or signals from the analog or DSP blocks.
In Figure 35, ADDR is the write address and data is the write
data to be written to the MMR. All write instructions finish within
one cycle.
The address field is seven bits wide, allowing access to registers
from Address 0x0 to address 0x1FC in the AFE register block. All
MMR accesses are 32 bits only. Byte and half word accesses are
forbidden. All accesses are implied write only. There is a direct
mapping between the address field and the MMR address. In
Figure 35, ADDR corresponds to Bits[8:2] of the 16-bit MMR
address.
To enable the sequencer, set the SEQEN bit in the SEQCON
register. Writing 0 to this bit disables the sequencer.
The rate at which the sequencer commands are executed is
provided in the SEQWRTMR bits in the SEQCON register.
When a write command is executed by the sequencer, the
sequencer performs the MMR write and then waits SEQWRTMR
clock cycles before fetching the next command in the sequence.
The effect is the same as a write command followed by a wait
command. The main purpose of this setup is to reduce code
size when generating arbitrary waveforms. The SEQWRTMR
bits do not have any effect following a wait or timeout command.
For example, when writing to the WGCON register directly
through the SPI interface, the address used is 0x2014. To write to
the same register using the sequencer, the address field must be
0b0000101 (Bits[8:2] of the address used by the external
controller).
The data field is 24 bits wide and only allows writing to the MMR
bits, Bits[23:0]. It is not possible to write to the full 32 bits of the
MMRs via the sequencer. However, Bits[31:24] are not used by
any of the MMRs. Therefore, all assigned MMR bits can be
written by the sequencer.
In addition to a single write command being followed by a wait
command, multiple write commands can be executed in succession
followed by a wait command. Any configuration can be set up
rapidly by the sequencer, regardless of the number of register
writes followed by a precisely executed delay.
The sequencer can also be paused by setting the SEQHALT bit
in the SEQCON register. This option applies to each function,
including FIFO operations, internal timers, and waveform
generation. Reads from the MMRs are allowed when the
sequencer is paused. This mode is intended for debugging
during software development.
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