ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
External Port Bus Request and Grant Cycle Timing
Table 35 and Table 36 on Page 52 and Figure 21 and Figure 22
on Page 52 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 35. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tBS
tBH
BR Asserted to CLKOUT Low Setup
5.0
0.0
ns
ns
CLKOUT Low to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
5.0
5.0
4.0
4.0
3.6
3.6
ns
ns
ns
ns
ns
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
CLKOUT Low to BG Asserted Output Delay
CLKOUT Low to BG Deasserted Output Hold
CLKOUT Low to BGH Asserted Output Delay
CLKOUT Low to BGH Deasserted Output Hold
tDBG
tEBG
tDBH
tEBH
CLKOUT
tBH
tBS
BR
tSD
tSE
AMSx
tSD
tSE
ADDR 19-1
ABE1-0
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
tEBH
BGH
Figure 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. C
|
Page 51 of 100
|
February 2010
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